Infrastructure-level exposure analysis across geographic, supplier, technology, and geopolitical dimensions. Exposure scores are modeled estimates — not predictions.
All figures are illustrative estimates only. Sourced from public announcements and analyst reports — approximated for demo purposes. Not for investment, trading, or business decisions.
~92% of sub-5nm global wafer capacity located in Taiwan. No viable alternative source at scale within 5 years. Structural single-point-of-failure for AI chip supply. [est.]
TSMC Arizona (N4) ramp underway. N2 Arizona planned. Intel 18A available by ~2026. Full mitigation timeline: 10+ years. [est.]
All NVIDIA Hopper/Blackwell and AMD MI300 GPUs require CoWoS-L advanced packaging exclusively from TSMC. No alternative packaging supplier for these configurations at scale. [est.]
TSMC capacity expanding through Chunan and Kaohsiung. Intel EMIB/Foveros for Intel chips. No third-party CoWoS equivalent. [est.]
U.S. lacks domestic CoWoS-equivalent advanced packaging at scale. AI GPU packaging remains Taiwan-centric. CHIPS Act packaging investments behind schedule. [est.]
Amkor OSAT Arizona facility in ramp. ASE U.S. investments. Intel Foveros domestic. Full readiness: 3–5 years. [est.]
SK Hynix supplies ~60% of HBM3e. Samsung and Micron ramping but constrained. NVIDIA H100/H200/B200 all depend on SK Hynix HBM3e. [est.]
Micron HBM4 ramp planned 2026. Samsung 8hi-stack HBM3 competing. Diversification underway but 2025 remains tight. [est.]
Ajinomoto Build-up Film (ABF) substrates dominated by Ibiden and Shinko. Critical component for all leading-edge flip-chip packages. Capacity expansion lags demand. [est.]
Ibiden and Shinko both investing in capacity. New players (Nanya, Semco) entering market. Easing expected 2025–2026. [est.]
Apple consumes ~45% of TSMC N3 capacity. NVIDIA Blackwell on N4P. AMD, MediaTek, Qualcomm competing for N2 allocation. Structural over-subscription risk 2025–2026. [est.]
TSMC capacity expansion 2025–2027 is the primary mitigation. Customer priority tiers reduce but don't eliminate risk. [est.]
Samsung 3GAE/3GAP yield rates remain below TSMC N3E benchmarks. Limited external customer adoption. Qualcomm returned to TSMC for Snapdragon 8 Gen 4. [est.]
SF2 (2nm-class) in development. Samsung investing heavily in process improvement. Timeline to TSMC parity: 2–3 years. [est.]
U.S./allied export controls on advanced chips (A100/H100/H800 equiv.) to China. China represents ~15–25% of global semiconductor market. Bifurcation of global AI supply chains. [est.]
NVIDIA China-specific SKUs (H20). SMIC domestic ramp ongoing. ASML equipment controls tightening. [est.]
Northern Virginia, Texas, and PNW datacenter markets approaching grid capacity limits. Power availability becoming primary constraint on new AI cluster buildout. [est.]
Nuclear partnerships (Constellation/Microsoft), gas peakers, DG Solar deployment. Build timelines extending 18–36 months. [est.]
U.S. CHIPS Act domestic fab construction depends on skilled workforce pipeline, equipment lead times, and permitting. Execution risk high — timelines may slip. [est.]
DOC disbursing grants. Construction underway at TSMC Arizona. Intel 18A ramp dependent on technology readiness. [est.]