Semiconductor, AI chip, packaging, and infrastructure terminology used throughout FabDashboard. 39 terms across 6 categories.
Short for fabrication plant. A semiconductor manufacturing facility where silicon wafers are processed into integrated circuits.
A company that manufactures semiconductor chips for other companies (fabless design firms). TSMC, Samsung Foundry, and GlobalFoundries are examples.
Integrated Device Manufacturer. A company that both designs and manufactures its own chips. Intel (historically) and Samsung are IDMs.
A chip design company that outsources all manufacturing to foundries. NVIDIA, AMD, Qualcomm, and Apple are fabless companies.
Outsourced Semiconductor Assembly and Test. Companies that handle chip packaging and testing after wafer fabrication. ASE and Amkor are major OSATs.
Wafer Starts Per Month. The primary metric for fab capacity. Measured in thousands of 300mm wafer equivalent starts per month.
The percentage of functional chips produced per wafer. Higher yield = lower cost per chip. Critical for profitability at leading-edge nodes.
The final step in chip design where the design data is sent to the foundry for mask creation. Typically costs $1M–$50M at leading-edge nodes.
Early-stage production before a node is fully qualified. Used to build initial inventory and identify yield issues before mass production.
A semiconductor manufacturing generation defined by feature size (nm). Smaller nm = denser, more efficient transistors. Modern 'nm' labels are marketing names, not literal measurements.
Fin Field-Effect Transistor. A 3D transistor architecture used from ~16nm through 3nm. Replaced planar transistors. Dominant architecture at 7nm, 5nm, 4nm, 3nm.
Gate-All-Around. Next-generation transistor architecture replacing FinFET at 2nm and below. Samsung SF2 and TSMC N2 use GAA variants (MBCFET and NanoFlex).
TSMC's 3nm-class process nodes. N3E is an enhanced version with better yield and power. Used in Apple A17 Pro, some NVIDIA Blackwell dies.
TSMC's 2nm-class node using NanoFlex GAA transistors. Mass production expected 2025. AMD, Apple, and NVIDIA are early adopters.
Intel's most advanced process node featuring RibbonFET (GAA) transistors and PowerVia (backside power delivery). Competing with TSMC N2 at leading edge.
Intel's backside power delivery technology. Routes power through the back of the wafer, freeing front-side routing for signals and improving power efficiency.
Extreme Ultraviolet Lithography. Uses 13.5nm wavelength light to pattern chip features. Required at 7nm and below. ASML is the sole supplier of EUV systems.
Next-generation EUV with higher numerical aperture (0.55 vs 0.33). Enables finer patterning for 2nm and below. ASML TWINSCAN EXE:5000.
Technologies for connecting multiple chips together in a single package at high bandwidth. Critical for AI chips that exceed the limits of single-die manufacturing.
Chip on Wafer on Substrate. TSMC's interposer-based 2.5D packaging technology. Used in NVIDIA H100, A100, and all Blackwell GPUs. Two variants: CoWoS-L (local) and CoWoS-S (substrate).
System on Integrated Chips. TSMC's 3D stacking technology enabling face-to-face or face-to-back chip bonding at very short interconnect distances.
A layer of silicon or glass between chips and substrate that provides dense interconnect routing. The 'bridge' between chiplets in 2.5D packaging.
Embedded Multi-die Interconnect Bridge. Intel's local silicon bridge packaging technology. Smaller, lower cost than full silicon interposer.
Intel's 3D face-to-face stacking technology. Enables very dense vertical integration between compute and memory dies.
A modular chip die designed to be integrated with other chiplets in a multi-chip package. Enables combining best-of-breed process nodes for different functions.
Universal Chiplet Interconnect Express. An open industry standard for chiplet-to-chiplet interconnects enabling cross-vendor chip integration.
High Bandwidth Memory. DRAM stacked vertically with a wide memory interface (1024-bit+). Provides massive bandwidth for AI training workloads. HBM3e is current generation.
Next-generation High Bandwidth Memory. Expected 2026. Higher bandwidth, larger stack capacity, required for NVIDIA Rubin-era GPUs.
South Korean memory manufacturer. World's leading supplier of HBM3e. Supplies NVIDIA's entire H100/H200/B200 HBM allocation.
Large cloud providers (AWS, Azure, Google Cloud, Meta) that operate at massive scale. Primary buyers of AI accelerators and builders of AI datacenters.
A group of AI accelerators (GPUs, TPUs) interconnected for large-scale model training or inference. Can range from thousands to hundreds of thousands of GPUs.
A high-bandwidth, low-latency networking technology used to interconnect GPUs within AI clusters. NVIDIA dominates through its Mellanox acquisition.
NVIDIA's proprietary high-bandwidth interconnect for GPU-to-GPU communication within a server node. NVL72 (72 GPUs) is current generation.
Thermal Design Power. The maximum sustained power a chip or system is designed to dissipate. Critical for datacenter power planning.
Tera Floating Point Operations Per Second. Measure of computational throughput. FP8/FP16/BF16 TFLOPS are common AI performance metrics.
Dutch company and sole manufacturer of EUV lithography systems. Critical single-point dependency for all leading-edge semiconductor manufacturing.
U.S. Creating Helpful Incentives to Produce Semiconductors Act (2022). $52.7B in grants and $24B in tax credits to incentivize domestic semiconductor manufacturing.
U.S. (BIS/EAR) restrictions on exporting advanced semiconductor equipment and chips to certain countries, particularly China.
The process by which a foundry or supplier assigns constrained capacity to customers. Priority allocation determines which customers get scarce chips first.